High speed serial interfaces, such as low-voltage differential signaling (LVDS) are increasingly being used to reduce interconnection between integrated circuits (ICs) and to lower electromagnetic (EM) and electrostatic (ES) radiation from circuit boards. These serial interfaces have sync generation and self-locking capability using only a clock reference, a phase locked loop (PLL), and a data bus for each receiver.
LVDS is a high-speed digital interface that is popular in applications that demand high data rate transmission with low power consumption and high noise immunity. Low-voltage differential signaling has been standardized under ANSI/TIA/EIA-644, EIA/TIA-644. LVDS is a differential balanced interface which can communicate data at speeds of better than 400 Mbps over a distance of 10 meters. Communication speeds and distances, however, are dependent on the type of cable, back plane, or circuit board carrying the LVDS signal.
A typical LVDS arrangement is shown in FIG. 1 in which a main board communicates with multiple system boards A-D via LVDS interfaces. Each LVDS interface employs a transmitter and receiver at each terminal end. FIG. 1 shows that each receiver (RX) is associated with a phase locked loop (PLL) which regenerates a clock signal from the received data, often utilizing both edge polarities. In addition,
FIG. 1 shows the path lengths connecting each terminal end of the system to be different, as depicted by symbols LA, LB, LC, and LD. Differences in phase due to these differing path lengths are accommodated by the individual PLLs associated with each receiver (RX). Consequently, the typical high speed serial interface arrangement shown in FIG. 1 requires four phase locked loops on the main board and one on each system board.
A typical low cost field programmable gate array (FPGA) cannot support the system architecture depicted in FIG. 1 due to the limited number of, for example, four phase locked loops that can be implemented on such an FPGA. This may limit the number of system boards that may be interfaced in an exemplary system or may necessitate running serial buses and PLLs at twice or three times the otherwise required frequency in order to achieve the required system bandwidth. This is a serious limitation when four or more serial buses are to be handled by a single IC. Typically, additional phase locked loops are utilized within the exemplary main controller board of FIG. 1 to provide a common clock to each transmitter and for other clocking and drive signals needed for other devices such as double data rate (DDR) memory.